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IEEE C37.118.1a-2014 Compliance Testing of EPLL and DFAC-PLL for Synchrophasors

Kumar, Puneet and Gurrala, Gurunath (2018) IEEE C37.118.1a-2014 Compliance Testing of EPLL and DFAC-PLL for Synchrophasors. In: North American Power Symposium (NAPS), SEP 09-11, 2018, Fargo, ND.

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Official URL: https://doi.org/10.1109/NAPS.2018.8600570

Abstract

Phase Locked Loop (PLL) methods are mainly used for frequency tracking and phase locking mechanism. Very few of the PLL methods are suggested in the literature for synchrophasor applications as they require estimation of amplitude along with the phase and frequency. In this paper compliance testing according to IEEE standard C37.118.1a-2014 is carried out for two PLL methods amenable for synchrophasor applications, namely enhanced PLL (EPLL) and double frequency & amplitude compensation PLL (DFAC-PLL).

Item Type: Conference Proceedings
Additional Information: North American Power Symposium (NAPS), Fargo, ND, SEP 09-11, 2018
Keywords: Synchrophasor; Phasor Measurement Unit (PMU); Phase Locked Loop (PLL); global positioning system (GPS)
Department/Centre: Division of Electrical Sciences > Electrical Engineering
Depositing User: Id for Latest eprints
Date Deposited: 06 Mar 2019 10:44
Last Modified: 06 Mar 2019 10:44
URI: http://eprints.iisc.ac.in/id/eprint/61910

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