A 0.9-5.4GHz wideband fast settling frequency synthesizer for 5G based consumer services

Zahir, Zaira and Banerjee, Gaurab (2018) A 0.9-5.4GHz wideband fast settling frequency synthesizer for 5G based consumer services. In: ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 97 (3, SI). pp. 565-577.

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Abstract

In this paper, a frequency synthesizer, based on a type-2, third order phase locked loop (PLL), covering the frequency range of 0.9-5.4 GHz using three voltage controlled oscillators, is implemented using a 0.13-lm CMOS technology. The PLL has three modes of operation-a high bandwidth mode, a low bandwidth mode and a dynamic mode, in which the bandwidth dynamically changes from a low to a high value, during a frequency jump, and reverts back to low value, once the PLL settles. With a proper choice of bandwidth and timing synchronization during a frequency jump, a worst-case settling time of 3-ls has been obtained, which is one of the lowest in reported literature. The input clock of the PLL is set to 100 MHz, but it can go as low as 25 MHz without having any effect on its settling time. The PLL consumes 24 mW of power and occupies 0.8 mm2 of active area. This PLL is expected to be specially useful in wide-bandwidth cognitive radios that require large and fast transitions in the frequency of operation.

Item Type:	Journal Article
Publication:	ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
Publisher:	SPRINGER
Additional Information:	Copy right for this article belong to SPRINGER
Keywords:	PLL; Fifth generation; Settling time; CMOS; Cognitive radios
Department/Centre:	Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited:	27 Nov 2018 15:44
Last Modified:	27 Nov 2018 15:44
URI:	http://eprints.iisc.ac.in/id/eprint/61164

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