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DFG partitioning algorithms for coarse grained reconfigurable array assisted RTL simulation accelerators

Mahapatra, Ipsita Biswas and Agarwal, Utkarsh and Nandy, SK (2018) DFG partitioning algorithms for coarse grained reconfigurable array assisted RTL simulation accelerators. In: IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), MAR 16-17, 2018, Bangalore, INDIA. (In Press)

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Official URL: http://dx.doi.org/10.1109/CONECCT.2018.8482367

Abstract

As the complexity of circuit design increases, verification of these circuits through simulation also becomes extremely challenging. This creates a bottleneck in the IC design process. Distributed simulation is one way of solving this problem where the simulation workload is distributed among the parallel processors involved in the simulation. However the design has to be carefully partitioned for this purpose. In order to perform distributed simulation, many efficient partitioning algorithms have been proposed till date. These algorithms mostly partition gate level netlist or logic circuits and reduces inter-processor communication by minimizing cutsize for a given constraint of load balance. In this paper, we present two different partitioning schemes for performing distributed simulation. They are: a Discrete Particle Swarm Optimization (DPSO) based partitioning algorithm (DPSO-PA) and an effective partitioning heuristic. These algorithms partitions Data Flow Graph (DFG) for a recently proposed Coarse Grained Reconfigurable Array assisted Hardware Accelerator (CGRA-HA). We also propose an improved version of the original DPSO methodology through careful selection of initial partition sets. It is found that the proposed heuristic based partitioning algorithm outperforms the modified DPSO-PA in terms of lesser cut-edges.

Item Type: Conference Proceedings
Additional Information: IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), Bangalore, INDIA, MAR 16-17, 2018
Keywords: CGRA; Hardware accelerator; RTL simulation; Distributed simulation; Data flow graph
Department/Centre: Division of Electrical Sciences > Computer Science & Automation
Depositing User: Id for Latest eprints
Date Deposited: 16 Nov 2018 15:33
Last Modified: 16 Nov 2018 15:33
URI: http://eprints.iisc.ac.in/id/eprint/61088

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