ePrints@IIScePrints@IISc Home | About | Browse | Latest Additions | Advanced Search | Contact | Help

Dielectric Engineering of HfO2 Gate-Stacks for Normally-ON GaN HEMTs on 200-mm Silicon Substrates

Chandrasekar, Hareesh and Kumar, Sandeep and Ganapathi, Kolla Lakshmi and Prabhu, Shreesha and Bin Dolmanan, Surani and Tripathy, Sudhiranjan and Raghavan, Srinivasan and Bhat, KN and Mohan, Sangeneni and Muralidharan, Rangarajan and Bhat, Navakanta and Nath, Digbijoy N (2018) Dielectric Engineering of HfO2 Gate-Stacks for Normally-ON GaN HEMTs on 200-mm Silicon Substrates. In: IEEE TRANSACTIONS ON ELECTRON DEVICES, 65 (9). pp. 3711-3718.

[img] PDF
Ieee_Tra_Ele_Dev_65-9_3711_2018.pdf - Published Version
Restricted to Registered users only

Download (2MB) | Request a copy
Official URL: http://dx.doi.org/10.1142/S0219199717500717

Abstract

We report on the band offset and interfacial electronic properties of e-beam evaporated HfO2 gate dielectrics on III-nitride device stacks on Si. A conduction band offset of 1.9 eV is extracted for HfO2/GaN along with a very low density of fixed bulk and interfacial charges for optimally annealed samples. Normally-ON HfO2/AIGaN/GaN metal-insulator-semiconductor highelectron-mobility transistors exhibit negligible shifts in threshold voltage, transconductances of 120 mS/mm for 3 mu m gate length devices, and three-terminal off-state gate leakage currents of 55 nA/mm at a V-D of 100 V. Dynamic capacitance dispersion measurements in the temperature range of 25 degrees C-200 degrees C show two peaks at the AIGaN/GaN interface corresponding to slow and fast interface traps with a peak D-it of 5.5 x 10(13) and 1.5 x 10(13) eV(-1) cm(-2) respectively as a function of Fermi level position above E-c . The HfO2/AIGaN interface exhibits a reasonably constant peak D-it of 2 x 10(13) _4.4 x 10(13) eV(-1) cm(-2) at trap levels of 0.42-0.72 eV below E-c. Hysteretic pulsed I-D-V-G measurements revealed a negative shift in threshold voltages indicative of unoccupied donor-like trap states at the HfO2/AIGaN interface and comparable D-it to that inferred from conductance measurements.

Item Type: Journal Article
Additional Information: Copy right for this article belong to IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA
Keywords: Band offset; conductance; dielectric engineering; GaN; high-electron-mobility transistor (HEMT); high-k dielectric; interface traps; pulsed-IV
Department/Centre: Division of Interdisciplinary Research > Centre for Nano Science and Engineering
Depositing User: Id for Latest eprints
Date Deposited: 11 Sep 2018 14:56
Last Modified: 25 Feb 2019 11:19
URI: http://eprints.iisc.ac.in/id/eprint/60648

Actions (login required)

View Item View Item