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On the Design Challenges of Drain Extended FinFETs for Advance SoC Integration

Kumar, B Sampath and Paul, Milova and Shrivastava, Mayank (2017) On the Design Challenges of Drain Extended FinFETs for Advance SoC Integration. In: International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), SEP 07-09, 2017, Kamakura, JAPAN, pp. 189-192.

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Official URL: https://doi.org/10.23919/SISPAD.2017.8085296

Abstract

In this paper, for the first time, challenges associated with high voltage drain extended device design in nanoscale FinFET technology is discussed in context of System on Chip (SoC) integration. Using 3D technology CAD, performance figures of merit matrix for integrated switching applications, quasi saturation, device scaling, ESD reliability, self-heating behavior and Safe Operating Area (SOA) concerns are comprehensively correlated/compared with planar drain extended MOS device.

Item Type: Conference Proceedings
Additional Information: Copyright of this article is belongs to IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Depositing User: Id for Latest eprints
Date Deposited: 02 Apr 2018 20:08
Last Modified: 02 Apr 2018 20:08
URI: http://eprints.iisc.ac.in/id/eprint/59493

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