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A Hardware Architecture for Radial Basis Function Neural Network Classifier

Mohammadi, Mahnaz and Krishna, Akhil and Nalesh, S and Nandy, S K (2018) A Hardware Architecture for Radial Basis Function Neural Network Classifier. In: IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 29 (3). pp. 481-495.

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Official URL: http://dx.doi.org/ 10.1109/TPDS.2017.2768366


In this paper we present design and analysis of scalable hardware architectures for training learning parameters of RBFNN to classify large data sets. We design scalable hardware architectures for K-means clustering algorithm to training the position of hidden nodes at hidden layer of RBFNN and pseudoinverse algorithm for weight adjustments at output layer. These scalable parallel pipelined architectures are capable of implementing data sets with no restriction on their dimensions. This paper also presents a flexible and scalable hardware accelerator for realization of classification using RBFNN, which puts no limitation on the dimension of the input data is developed. We report FPGA synthesis results of our implementations. We compare results of our hardware accelerator with CPU, GPU and implementations of the same algorithms and with other existing algorithms. Analysis of these results show that scalability of our hardware architecture makes it favorable solution for classification of very large data sets.

Item Type: Journal Article
Additional Information: Copy right for the article belong to IEEE COMPUTER SOC, 10662 LOS VAQUEROS CIRCLE, PO BOX 3014, LOS ALAMITOS, CA 90720-1314 USA
Department/Centre: Division of Interdisciplinary Research > Supercomputer Education & Research Centre
Depositing User: Id for Latest eprints
Date Deposited: 08 Mar 2018 19:09
Last Modified: 08 Mar 2018 19:09
URI: http://eprints.iisc.ac.in/id/eprint/59105

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