Improving Area Efficiency of Residue Number System Based Implementation of DSP Algorithms

Mahesh, MN and Mehendale, Mahesh (1999) Improving Area Efficiency of Residue Number System Based Implementation of DSP Algorithms. In: Twelfth International Conference On VLSI Design, 1999, 7-10 January, Goa, India, pp. 340-345.

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Abstract

In applications, such as high quality audio, that need more than 16 bits of precision, the processing of signals on a 16-bit DSP requires double precision computation and is hence time consuming. Since in Residue Number System (RNS), the high precision data is decomposed to lower precision for its processing, in this paper, we propose RNS for increasing the performance of such applications implemented on a single processor. We apply multirate architectures and also suggest some architectural extensions to the processor to further enhance the performance. The results show that performance improvement of more than 57% can be achieved with these implementations. We also show that the power dissipation can be significantly reduced with such implementations.

Item Type:	Conference Paper
Publisher:	IEEE
Additional Information:	Copyright 1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre:	Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited:	09 Mar 2006
Last Modified:	19 Sep 2010 04:24
URI:	http://eprints.iisc.ac.in/id/eprint/5867

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