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A Very High Resolution Stacked Multilevel Inverter Topology for Adjustable Speed Drives

Nair, Viju R and Gopakumar, K and Franquelo, Leopoldo G (2018) A Very High Resolution Stacked Multilevel Inverter Topology for Adjustable Speed Drives. In: IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 65 (3). pp. 2049-2056.

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Official URL: http://dx.doi.org/10.1109/TIE.2017.2739702

Abstract

This paper proposes a novel 49-level stacked inverter topology for drives. The 49 levels are achieved by stacking three 17-level inverters. Each of the 17-level inverter is developed by cascading a flying capacitor (FC) inverter with three capacitor-fed H-bridges. The device count can be reduced by making the FC and the three cascaded H-bridges common to the dc link in each phase using selector switches in between them. The selector switches need to operate at fundamental frequency only. Also, the devices need to block very low voltages. Hence, MOSFETs can be used. This topology requires three dc sources, each of Vdc/6 only, which can be replaced with stacked batteries for electric vehicle applications. The reduction in the dc voltage requirement is achieved by using a normal symmetric six-phase induction motor with parallel connection of the opposite phase windings. All the floating capacitors in the topology can be balanced irrespective of any modulation index or load power factor. Due to the high number of voltage levels, nearest level control can be used instead of pulse width modulation, which reduces the switching losses. The dv/dt during the inverter operation is also less. Detailed experimental results at different speeds of operation and during transients ensure that the novel topology can be a viable option for high-power adjustable speed drives.

Item Type: Journal Article
Additional Information: Copy right for this article belongs to the IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Depositing User: review EPrints Reviewer
Date Deposited: 12 Jan 2018 09:42
Last Modified: 12 Jan 2018 09:42
URI: http://eprints.iisc.ac.in/id/eprint/58636

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