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Performance and Reliability Codesign for Superjunction Drain Extended MOS Devices

Somayaji, Jhnanesh and Kumar, Sampath B and Bhat, M S and Shrivastava, Mayank (2017) Performance and Reliability Codesign for Superjunction Drain Extended MOS Devices. In: IEEE TRANSACTIONS ON ELECTRON DEVICES, 64 (10). pp. 4175-4183.

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Official URL: http://doi.org/10.1109/TED.2017.2733043

Abstract

Conventionally, integrated drain-extended MOS (DeMOS) like high-voltage devices are designed while keeping only performance targets for a given application in mind. In this paper, for the first time, performance and reliability codesign approach using 3-D TCAD has been presented for various superjunction (SJ) type DeMOS devices. In this context, how to effectively utilize the SJ concept in a DeMOS device for System on Chip applications, which often has stringent switching and RF performance targets, is explored in detail in this paper. Moreover, design and reliability tradeoffs for switching and RF applications are discussed, while considering two unique sets, one with fixed breakdown voltage and other with fixed ON-resistance. Finally, hot carrier generation, safe operating area concerns, and electrostatic discharge physics are explored and compared using 3-D TCAD simulations.

Item Type: Journal Article
Additional Information: Copy right for this article belongs to the IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Depositing User: Id for Latest eprints
Date Deposited: 01 Dec 2017 06:51
Last Modified: 01 Dec 2017 06:51
URI: http://eprints.iisc.ac.in/id/eprint/58359

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