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Using Reconfigurable Multi-Core Architectures for Safety-Critical Embedded Systems

Guillaumet, Tom and Sharma, Aayush and Feron, Eric and Krishna, Madhava and Narayan, Ranjani and Baufreton, Philippe and Neumann, Francois and Grolleau, Emmanuel (2016) Using Reconfigurable Multi-Core Architectures for Safety-Critical Embedded Systems. In: 35th IEEE/AIAA Digital Avionics Systems Conference (DASC), SEP 25-29, 2016, Sacramento, CA.

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Official URL: http://dx.doi.org/ 10.1109/DASC.2016.7777978

Abstract

With the onset of multi-and many-core chips, the single-core market is closing down. Those chips constitute a new challenge for aerospace and safety-critical industries in general. Little is known about the certification of software running on these systems. There is therefore a strong need for developing software architectures based on multi-core architectures, yet compliant with safety-criticality constraints. This paper presents a reconfigurable multi-core architecture and the safety-criticality constraints for airborne systems. The last section uses the current certification guidance to explain how the architecture can satisfy these constraints even with dynamic features activated.

Item Type: Conference Proceedings
Additional Information: Copy right for this article belongs to the IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
Department/Centre: Division of Interdisciplinary Research > Supercomputer Education & Research Centre
Depositing User: Id for Latest eprints
Date Deposited: 31 Jan 2017 05:31
Last Modified: 31 Jan 2017 05:31
URI: http://eprints.iisc.ac.in/id/eprint/56137

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