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MicroRefresh: Minimizing Refresh Overhead in DRAM Caches

Gulur, Nagendra and Govindarajan, R and Mehendale, Mahesh (2016) MicroRefresh: Minimizing Refresh Overhead in DRAM Caches. In: International Symposium on Memory Systems (MEMSYS), OCT 03-06, 2016, Washington, DC, pp. 350-361.

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Official URL: http://dx.doi.org/10.1145/2989081.2989100

Abstract

DRAM memory systems require periodic recharging to avoid loss of data from leaky capacitors. These refresh operations consume energy and reduce the duration of time for which the DRAM banks are available to service memory requests. Higher DRAM density and 3D-stacking aggravate the refresh overheads, incurring even higher energy and performance costs. 3D-stacked DRAM and other emerging on chip High Bandwidth Memory (HBM) technologies which are widely considered to be changing the landscape of memory hierarchy in future heterogeneous and many-core architectures could suffer significantly from refresh overheads. Such large on-chip memory, when used as a very large last level cache, however, provides opportunities for addressing the refresh overheads. In this work, we propose MicroRefresh, a scheme for almost eliminating the refresh overhead in DRAM caches. MicroRefresh eliminates unwanted refresh of recently accessed DRAM pages; it takes advantage of the relative latency difference between on-chip and off-chip DRAM and achieves a fine balance of usage of system resources by aggressively opportunistically eliminating refresh of older DRAM pages. It tolerates any resulting increase in cache misses by leveraging the under-utilized main memory bandwidth. The resulting organization eliminates the energy and performance overhead of refresh operations in the DRAM cache to achieve overall performance and energy improvement. Across both 4-core and 8-core workloads, MicroRefresh eliminates 92% the refresh energy consumed in the baseline periodic refresh mechanism. Further this is accompanied by performance improvements of upto 10%, with average improvements of 3.9% and 3.4% in 4-core and 8-core respectively.

Item Type: Conference Proceedings
Additional Information: Copy right for this article belongs to the ASSOC COMPUTING MACHINERY, 1515 BROADWAY, NEW YORK, NY 10036-9998 USA
Department/Centre: Division of Interdisciplinary Research > Supercomputer Education & Research Centre
Depositing User: Id for Latest eprints
Date Deposited: 31 Jan 2017 05:25
Last Modified: 31 Jan 2017 05:25
URI: http://eprints.iisc.ac.in/id/eprint/55995

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