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A 3.2 mW 0.13 mu m High Sensitivity Frequency-domain CMOS Capacitance Interface

Gaggatur, Javed S and Dixena, Pradeep K and Banerjee, Gaurab (2016) A 3.2 mW 0.13 mu m High Sensitivity Frequency-domain CMOS Capacitance Interface. In: IEEE International Symposium on Circuits and Systems (ISCAS), MAY 22-25, 2016, Montreal, CANADA, pp. 1070-1073.

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Official URL: http://dx.doi.org/10.1109/ISCAS.2016.7527429


A frequency domain capacitance interface system is proposed for a femto-farad capacitance measurement. In this technique, a ring oscillator circuit is used to generate a change in time period, due to a change in the sensor capacitance. The time-period difference of two such oscillators is compared and is read-out using a phase frequency detector and a charge pump. The output voltage of the system, is proportional to the change in the input sensor capacitance. The capacitance sensor interface system was designed and a prototype was implemented in a 0.13 mu m standard CMOS technology. Experimental and simulation results are presented. It exhibits a maximum sensitivity of 8.1 mV/fF, which is significant improvement over the state-of-the-art while consuming 3.2 mW from a 1.2 V supply.

Item Type: Conference Proceedings
Additional Information: Copy right for this article belongs to the IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
Department/Centre: Division of Electrical Sciences > Electrical Communication Engineering
Depositing User: Id for Latest eprints
Date Deposited: 31 Jan 2017 05:24
Last Modified: 31 Jan 2017 05:24
URI: http://eprints.iisc.ac.in/id/eprint/55989

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