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An Efficient Design of 4-Bit Serial Input Parallel Output/Serial Output Shift Register in Quantum Dot Cellular Automata

Padmanabhan, Ashwin and Miranda, Allen Vivean and Srinivas, T (2016) An Efficient Design of 4-Bit Serial Input Parallel Output/Serial Output Shift Register in Quantum Dot Cellular Automata. In: 3rd International Conference on Computing for Sustainable Global Development (INDIACom), MAR 16-18, 2016, New Delhi, INDIA, pp. 2736-2738.

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Official URL: http://ieeexplore.ieee.org/document/7724760/

Abstract

The VLSI technology that is in place today caters to almost all technology based products but as the need for speed and space increases VLSI technology might not be able to keep up with the demand. There are a lot of alternatives that are being researched on but very few can match VLSI in terms of performance. Technologies such as nanotechnology, photonics, quantum computing look promising in that regard.Quantum-dot Cellular Automata(QCA) is one such technology which possibly can replace VLSI at the same time provides higher processing speed while occupying lesser space. In this paper we propose a design for(I])Serial Input Parallel Output (SIPO)and ((I])serial Input Serial Output (SISO) registers with the help of QCA technology Keywords Shift register, Quantum dot, QCA technology

Item Type: Conference Proceedings
Additional Information: Copy right for this article belongs to the IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
Department/Centre: Division of Electrical Sciences > Electrical Communication Engineering
Depositing User: Id for Latest eprints
Date Deposited: 21 Jan 2017 08:40
Last Modified: 21 Jan 2017 08:40
URI: http://eprints.iisc.ac.in/id/eprint/55949

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