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Design of a Fast Response Time Single-Phase PLL with DC Offset Rejection Capability

Kulkarni, Abhijit and John, Vinod (2016) Design of a Fast Response Time Single-Phase PLL with DC Offset Rejection Capability. In: 31st Annual IEEE Applied Power Electronics Conference and Exposition (APEC), MAR 20-24, 2016, Long Beach, CA, pp. 2200-2206.

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Official URL: http://dx.doi.org/10.1109/APEC.2016.7468172

Abstract

Second-order generalized integrator (SOGI) based phase-locked loops (PLLs) are commonly used for grid voltage synchronization in single-phase grid-connected power converters. SOGI-PLLs are attractive because of their simple structure that makes them suitable for implementation even in low-end digital controllers. In this paper, an SOGI based fixed-parameter PLL structure with full dc offset rejection capability is presented. This PLL uses two cascaded SOGI structures and it is termed as cascaded generalized integrator PLL (CGI-PLL). A systematic design procedure is proposed for the CGI-PLL minimizing the response time and unit vector harmonic distortion. This design achieves minimum settling time for any given worst-case frequency deviation in the grid voltage and ensures that the unit vector THD is less than 1%. The PLL designed using the proposed method has sufficient harmonic attenuation capability. The steady-state and transient response of this PLL have been validated experimentally and are found to agree with the theoretical analysis.

Item Type: Conference Proceedings
Additional Information: Copy right for this article belongs to the IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
Department/Centre: Division of Electrical Sciences > Electrical Engineering
Depositing User: Id for Latest eprints
Date Deposited: 04 Jan 2017 05:09
Last Modified: 04 Jan 2017 05:09
URI: http://eprints.iisc.ac.in/id/eprint/55731

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