A 0.1-3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS

Raja, Immanuel and Banerjee, Gaurab and Zeidan, Mohamad A and Abraham, Jacob A (2016) A 0.1-3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS. In: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 24 (5). pp. 1975-1983.

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Abstract

A duty-cycle correction technique using a novel pulsewidth modification cell is demonstrated across a frequency range of 100 MHz-3.5 GHz. The technique works at frequencies where most digital techniques implemented in the same technology node fail. An alternative method of making time domain measurements such as duty cycle and rise/fall times from the frequency domain data is introduced. The data are obtained from the equipment that has significantly lower bandwidth than required for measurements in the time domain. An algorithm for the same has been developed and experimentally verified. The correction circuit is implemented in a 0.13-mu m CMOS technology and occupies an area of 0.011 mm(2). It corrects to a residual error of less than 1%. The extent of correction is limited by the technology at higher frequencies.

Item Type:	Journal Article
Publication:	IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Publisher:	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Additional Information:	Copy right for this article belongs to the IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA
Keywords:	50% duty cycle; CMOS; correction loop; duty-cycle correction (DCC); duty-cycle measurements; frequency domain measurements; rise/fall time measurements
Department/Centre:	Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited:	11 Jun 2016 05:02
Last Modified:	11 Jun 2016 05:02
URI:	http://eprints.iisc.ac.in/id/eprint/53884

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