ePrints@IIScePrints@IISc Home | About | Browse | Latest Additions | Advanced Search | Contact | Help

SMO: An Integrated Approach to Intra-array and Inter-array Storage Optimization

Bhaskaracharya, Somashekaracharya G and Bondhugula, Uday and Cohen, Albert (2016) SMO: An Integrated Approach to Intra-array and Inter-array Storage Optimization. In: ACM SIGPLAN NOTICES, 51 (1). pp. 526-538.

[img] PDF
ACM_Sig_Not_51-1_526_2016.pdf - Published Version
Restricted to Registered users only

Download (491kB) | Request a copy
Official URL: http://dx.doi.org/10.1145/2837614.2837636

Abstract

The polyhedral model provides an expressive intermediate representation that is convenient for the analysis and subsequent transformation of affine loop nests. Several heuristics exist for achieving complex program transformations in this model. However, there is also considerable scope to utilize this model to tackle the problem of automatic memory footprint optimization. In this paper, we present a new automatic storage optimization technique which can be used to achieve both intra-array as well as inter-array storage reuse with a pre-determined schedule for the computation. Our approach works by finding statement-wise storage partitioning hyper planes that partition a unified global array space so that values with overlapping live ranges are not mapped to the same partition. Our heuristic is driven by a fourfold objective function which not only minimizes the dimensionality and storage requirements of arrays required for each high-level statement, but also maximizes inter statement storage reuse. The storage mappings obtained using our heuristic can be asymptotically better than those obtained by any existing technique. We implement our technique and demonstrate its practical impact by evaluating its effectiveness on several benchmarks chosen from the domains of image processing, stencil computations, and high-performance computing.

Item Type: Journal Article
Additional Information: Copy right for this article belongs to the ASSOC COMPUTING MACHINERY, 2 PENN PLAZA, STE 701, NEW YORK, NY 10121-0701 USA
Keywords: Compilers; storage mapping optimization; memory optimization; array contraction; polyhedral framework
Department/Centre: Division of Electrical Sciences > Computer Science & Automation
Depositing User: Id for Latest eprints
Date Deposited: 17 May 2016 05:13
Last Modified: 17 May 2016 05:13
URI: http://eprints.iisc.ac.in/id/eprint/53837

Actions (login required)

View Item View Item