Part II: A Fully Integrated RF PA in 28-nm CMOS With Device Design for Optimized Performance and ESD Robustness

Gupta, Ankur and Shrivastava, Mayank and Baghini, Maryam Shojaei and Chandorkar, AN and Gossner, Harald and Rao, Ramgopal V (2015) Part II: A Fully Integrated RF PA in 28-nm CMOS With Device Design for Optimized Performance and ESD Robustness. In: IEEE TRANSACTIONS ON ELECTRON DEVICES, 62 (10). pp. 3176-3183.

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Abstract

In this paper, we report drain-extended MOS device design guidelines for the RF power amplifier (RF PA) applications. A complete RF PA circuit in a 28-nm CMOS technology node with the matching and biasing network is used as a test vehicle to validate the RF performance improvement by a systematic device design. A complete RF PA with 0.16-W/mm power density is reported experimentally. By simultaneous improvement of device-circuit performance, 45% improvement in the circuit RF power gain, 25% improvement in the power-added efficiency at 1-GHz frequency, and 5x improvement in the electrostatic discharge robustness are reported experimentally.

Item Type:	Journal Article
Publication:	IEEE TRANSACTIONS ON ELECTRON DEVICES
Publisher:	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Additional Information:	Copy right for this article belongs to the IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA
Keywords:	CMOS; device-circuit codesign; drain-extended MOS (DeMOS); electrostatic discharge (ESD); power amplifier (PA); RF; shallow-trench-isolation (STI); system-on-chip (SoC)
Department/Centre:	Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited:	30 Oct 2015 07:09
Last Modified:	30 Oct 2015 07:09
URI:	http://eprints.iisc.ac.in/id/eprint/52586

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