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Timing Recovery Algorithms and Architectures for 2-D Magnetic Recording Systems

Reddy, Brijesh P and Srinivasa, Shayan Garani and Dahandeh, Shafa (2015) Timing Recovery Algorithms and Architectures for 2-D Magnetic Recording Systems. In: 25th Magnetic Recording Conference (TMRC), AUG 11-14, 2014, Berkeley, CA.

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Official URL: http://dx.doi.org/ 10.1109/TMAG.2014.2361619

Abstract

We investigate the problem of timing recovery for 2-D magnetic recording (TDMR) channels. We develop a timing error model for TDMR channel considering the phase and frequency offsets with noise. We propose a 2-D data-aided phase-locked loop (PLL) architecture for tracking variations in the position and movement of the read head in the down-track and cross-track directions and analyze the convergence of the algorithm under non-separable timing errors. We further develop a 2-D interpolation-based timing recovery scheme that works in conjunction with the 2-D PLL. We quantify the efficiency of our proposed algorithms by simulations over a 2-D magnetic recording channel with timing errors.

Item Type: Conference Proceedings
Additional Information: Copy right for this article belongs to the IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA
Keywords: 2-D interpolation timing recovery; 2-D phase-locked loop (PLL); timing recovery; timing recovery for 2-D magnetic recording (TDMR)
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Depositing User: Id for Latest eprints
Date Deposited: 26 Jun 2015 07:34
Last Modified: 26 Jun 2015 07:34
URI: http://eprints.iisc.ac.in/id/eprint/51783

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