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Operand Isolation Circuits with Reduced Overhead for Low Power Data-Path Design

Siddhu, Lokesh and Mishra, Amit and Singh, Virendra (2014) Operand Isolation Circuits with Reduced Overhead for Low Power Data-Path Design. In: 27th International Conference on VLSI Design / 13th International Conference on Embedded Systems (VLSID), JAN 05-09, 2014, Mumbai, INDIA, pp. 483-488.

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Official URL: http://dx.doi.org/10.1109/VLSID.2014.90

Abstract

Dynamic power dissipation due to redundant switching is an important metric in data-path design. This paper focuses on the use of ingenious operand isolation circuits for low power design. Operand isolation attempts to reduce switching by clamping or latching the output of a first level of combinational circuit. This paper presents a novel method using power supply switching wherein both PMOS and NMOS stacks of a circuit are connected to the same power supply. Thus, the output gets clamped or latched to the power supply value with minimal leakage. The proposed circuits make use of only two transistors to clamp the entire Multiple Input Multiple Output (MIMO) block. Also, the latch-based designs have higher drive strength in comparison to the existing methods. Simulation results have shown considerable area reduction in comparison to the existing techniques without increasing timing overhead.

Item Type: Conference Proceedings
Additional Information: 27th International Conference on VLSI Design / 13th International Conference on Embedded Systems (VLSID), Mumbai, INDIA, JAN 05-09, 2014
Keywords: Low Power Design; Operand Isolation; Power Supply Switching
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Depositing User: Id for Latest eprints
Date Deposited: 21 Apr 2015 07:33
Last Modified: 21 Apr 2015 07:33
URI: http://eprints.iisc.ac.in/id/eprint/51335

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