Multithreaded Test Synthesis for Deadlock Detection

Samak, Malavika and Ramanathan, Murali Krishna (2015) Multithreaded Test Synthesis for Deadlock Detection. In: ACM SIGPLAN NOTICES, 49 (10). pp. 473-489.

PDF acm_sig_pla_49-10_473_2014.pdf - Published Version Restricted to Registered users only Download (553kB) | Request a copy

Abstract

Designing and implementing thread-safe multithreaded libraries can be a daunting task as developers of these libraries need to ensure that their implementations are free from concurrency bugs, including deadlocks. The usual practice involves employing software testing and/or dynamic analysis to detect. deadlocks. Their effectiveness is dependent on well-designed multithreaded test cases. Unsurprisingly, developing multithreaded tests is significantly harder than developing sequential tests for obvious reasons. In this paper, we address the problem of automatically synthesizing multithreaded tests that can induce deadlocks. The key insight to our approach is that a subset of the properties observed when a deadlock manifests in a concurrent execution can also be observed in a single threaded execution. We design a novel, automatic, scalable and directed approach that identifies these properties and synthesizes a deadlock revealing multithreaded test. The input to our approach is the library implementation under consideration and the output is a set of deadlock revealing multithreaded tests. We have implemented our approach as part of a tool, named OMEN1. OMEN is able to synthesize multithreaded tests on many multithreaded Java libraries. Applying a dynamic deadlock detector on the execution of the synthesized tests results in the detection of a number of deadlocks, including 35 real deadlocks in classes documented as thread-safe. Moreover, our experimental results show that dynamic analysis on multithreaded tests that are either synthesized randomly or developed by third-party programmers are ineffective in detecting the deadlocks.

Item Type:	Journal Article
Publication:	ACM SIGPLAN NOTICES
Publisher:	ASSOC COMPUTING MACHINERY
Additional Information:	Copy right for this article belongs to the ASSOC COMPUTING MACHINERY, 2 PENN PLAZA, STE 701, NEW YORK, NY 10121-0701 USA
Keywords:	Deadlock detection; dynamic analysis; concurrency
Department/Centre:	Division of Electrical Sciences > Computer Science & Automation
Date Deposited:	04 Mar 2015 12:50
Last Modified:	04 Mar 2015 12:50
URI:	http://eprints.iisc.ac.in/id/eprint/51001

Actions (login required)

View Item