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A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths

Das, Saptarsi and Madhu, Kavitha and Krishna, Madhav and Sivanandan, Nalesh and Merchant, Farhad and Natarajan, Santhi and Biswas, Ipsita and Pulli, Adithya and Nandy, SK and Narayan, Ranjani (2014) A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths. In: JOURNAL OF SYSTEMS ARCHITECTURE, 60 (7). pp. 592-614.

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Official URL: http://dx.doi.org/ 10.1016/j.sysarc.2014.06.002

Abstract

In this paper we present a framework for realizing arbitrary instruction set extensions (IE) that are identified post-silicon. The proposed framework has two components viz., an IE synthesis methodology and the architecture of a reconfigurable data-path for realization of the such IEs. The IE synthesis methodology ensures maximal utilization of resources on the reconfigurable data-path. In this context we present the techniques used to realize IEs for applications that demand high throughput or those that must process data streams. The reconfigurable hardware called HyperCell comprises a reconfigurable execution fabric. The fabric is a collection of interconnected compute units. A typical use case of HyperCell is where it acts as a co-processor with a host and accelerates execution of IEs that are defined post-silicon. We demonstrate the effectiveness of our approach by evaluating the performance of some well-known integer kernels that are realized as IEs on HyperCell. Our methodology for realizing IEs through HyperCells permits overlapping of potentially all memory transactions with computations. We show significant improvement in performance for streaming applications over general purpose processor based solutions, by fully pipelining the data-path. (C) 2014 Elsevier B.V. All rights reserved.

Item Type: Journal Article
Additional Information: Copy right for this article belongs to the ELSEVIER SCIENCE BV, PO BOX 211, 1000 AE AMSTERDAM, NETHERLANDS
Keywords: Reconfigurable computing; Instruction extension; Architecture exploration; Hardware data-path; Application acceleration
Department/Centre: Division of Biological Sciences > Central Animal Facility (Formerly Primate Research Laboratory)
Depositing User: Id for Latest eprints
Date Deposited: 24 Sep 2014 05:52
Last Modified: 24 Sep 2014 05:52
URI: http://eprints.iisc.ac.in/id/eprint/49942

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