ePrints@IIScePrints@IISc Home | About | Browse | Latest Additions | Advanced Search | Contact | Help

Design of a Low Power 64 Point FFT Architecture for WLAN Applications

Kala, S and Nalesh, S and Nandy, SK and Narayan, Ranjani (2013) Design of a Low Power 64 Point FFT Architecture for WLAN Applications. In: 25th International Conference on Microelectronics (ICM), DEC 15-18, 2013, Beirut, LEBANON.

[img] PDF
25th_int_con_mic_2013.pdf - Published Version
Restricted to Registered users only

Download (1MB) | Request a copy
Official URL: http://dx.doi.org/10.1109/ICM.2013.6734951

Abstract

This paper presents a Radix-4(3) based FFT architecture suitable for OFDM based WLAN applications. The radix-4(3) parallel unrolled architecture presented here, uses a radix-4 butterfly unit which takes all four inputs in parallel and can selectively produce one out of the four outputs. A 64 point FFT processor based on the proposed architecture has been implemented in UMC 130nm 1P8M CMOS process with a maximum clock frequency of 100 MHz and area of 0.83mm(2). The proposed processor provides a throughput of four times the clock rate and can finish one 64 point FFT computation in 16 clock cycles. For IEEE 802.11a/g WLAN, the processor needs to be operated at a clock rate of 5 MHz with a power consumption of 2.27 mW which is 27% less than the previously reported low power implementations.

Item Type: Conference Proceedings
Additional Information: copyright for this article belongs to IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
Keywords: Fast Fourier Transform; Radix-4(3); VLSI
Department/Centre: Division of Interdisciplinary Research > Supercomputer Education & Research Centre
Depositing User: Id for Latest eprints
Date Deposited: 03 Jun 2014 08:25
Last Modified: 03 Jun 2014 08:25
URI: http://eprints.iisc.ac.in/id/eprint/49085

Actions (login required)

View Item View Item