Time-Based All-Digital Technique for Analog Built-in Self-Test

Vasudevamurthy, Rajath and Das, Pratap Kumar and Amrutur, Bharadwaj (2014) Time-Based All-Digital Technique for Analog Built-in Self-Test. In: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 22 (2). pp. 334-342.

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Abstract

A scheme for built-in self-test of analog signals with minimal area overhead for measuring on-chip voltages in an all-digital manner is presented. The method is well suited for a distributed architecture, where the routing of analog signals over long paths is minimized. A clock is routed serially to the sampling heads placed at the nodes of analog test voltages. This sampling head present at each test node, which consists of a pair of delay cells and a pair of flip-flops, locally converts the test voltage to a skew between a pair of subsampled signals, thus giving rise to as many subsampled signal pairs as the number of nodes. To measure a certain analog voltage, the corresponding subsampled signal pair is fed to a delay measurement unit to measure the skew between this pair. The concept is validated by designing a test chip in a UMC 130-nm CMOS process. Sub-millivolt accuracy for static signals is demonstrated for a measurement time of a few seconds, and an effective number of bits of 5.29 is demonstrated for low-bandwidth signals in the absence of sample-and-hold circuitry.

Item Type:	Journal Article
Publication:	IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Publisher:	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Additional Information:	Copyright for this article belongs to the IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC,USA
Keywords:	Built-in self-test (BIST); current-starved; oversampling ratio; quantization; subsampling
Department/Centre:	Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited:	25 Feb 2014 08:33
Last Modified:	25 Feb 2014 08:33
URI:	http://eprints.iisc.ac.in/id/eprint/48459

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