Mixed-Mode Simulation Approach to Characterize the Circuit Delay Sensitivity to Implant Dose Variations

Srinivasaiah, HC and Bhat, Navakanta (2003) Mixed-Mode Simulation Approach to Characterize the Circuit Delay Sensitivity to Implant Dose Variations. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22 (6). 742 -747.

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Abstract

Process, device, and mixed-mode (device/circuit) simulation-based approach is presented for $0.1\mu{m}$ gate length CMOS technology optimization and sensitivity analysis. The disposable spacer-based $0.1\mu{m}$ NMOS and PMOS transistors with excellent short channel characteristics are designed using process and device simulations. The implant-dose sensitivity of the device parameters around the nominal value are estimated. The halo implant and super steep retrograde channel implant dose fluctuations are found to have a profound effect on device characteristics. It is shown that the mixed-mode device/circuit simulation can be used as an excellent tool to connect the circuit delay sensitivity to underlying process parameters. The simulation results demonstrate that the relation between circuit and process parameters is highly nonlinear for the deep submicron technology.

Item Type:	Journal Article
Publication:	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publisher:	IEEE
Additional Information:	�©1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Keywords:	Circuit delay;CMOS technology;Disposable Spacer;Mixed-mode simulation;Sensitivity analysis
Department/Centre:	Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited:	21 Dec 2005
Last Modified:	19 Sep 2010 04:22
URI:	http://eprints.iisc.ac.in/id/eprint/4705

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