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Tiling stencil computations to maximize parallelism

Bandishti, Vinayaka and Pananilath, Irshad and Bondhugula, Uday (2012) Tiling stencil computations to maximize parallelism. In: 12 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis, 2012, New York.

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Official URL: http://dl.acm.org/citation.cfm?id=2389051

Abstract

Most stencil computations allow tile-wise concurrent start, i.e., there always exists a face of the iteration space and a set of tiling hyperplanes such that all tiles along that face can be started concurrently. This provides load balance and maximizes parallelism. However, existing automatic tiling frameworks often choose hyperplanes that lead to pipelined start-up and load imbalance. We address this issue with a new tiling technique that ensures concurrent start-up as well as perfect load-balance whenever possible. We first provide necessary and sufficient conditions on tiling hyperplanes to enable concurrent start for programs with affine data accesses. We then provide an approach to find such hyperplanes. Experimental evaluation on a 12-core Intel Westmere shows that our code is able to outperform a tuned domain-specific stencil code generator by 4% to 27%, and previous compiler techniques by a factor of 2x to 10.14x.

Item Type: Conference Paper
Additional Information: Copyright of this article belongs to IEEE.
Keywords: Compilers; Program Transformation
Department/Centre: Division of Electrical Sciences > Computer Science & Automation
Depositing User: Francis Jayakanth
Date Deposited: 10 Jun 2013 08:01
Last Modified: 10 Jun 2013 08:01
URI: http://eprints.iisc.ac.in/id/eprint/46676

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