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Accelerating Reduction for Enabling Fast Multiplication over Large Binary Fields

Das, Saptarsi and Narayan, Ranjani and Narayan, Soumitra Kumar (2012) Accelerating Reduction for Enabling Fast Multiplication over Large Binary Fields. In: 8th International Joint Conference on e-Business and Telecommunications, JUL 18-21, 2011, Seville, SPAIN , pp. 249-263.

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Official URL: http://dx.doi.org/10.1007/978-3-642-35755-8_18

Abstract

In this paper we present a hardware-software hybrid technique for modular multiplication over large binary fields. The technique involves application of Karatsuba-Ofman algorithm for polynomial multiplication and a novel technique for reduction. The proposed reduction technique is based on the popular repeated multiplication technique and Barrett reduction. We propose a new design of a parallel polynomial multiplier that serves as a hardware accelerator for large field multiplications. We show that the proposed reduction technique, accelerated using the modified polynomial multiplier, achieves significantly higher performance compared to a purely software technique and other hybrid techniques. We also show that the hybrid accelerated approach to modular field multiplication is significantly faster than the Montgomery algorithm based integrated multiplication approach.

Item Type: Conference Proceedings
Additional Information: Copyright for this article belongs to the SPRINGER-VERLAG BERLIN, GERMANY.
Keywords: Elliptic curve cryptography; Binary fields; Reduction; Polynomial multiplication
Department/Centre: Division of Interdisciplinary Research > Supercomputer Education & Research Centre
Depositing User: Francis Jayakanth
Date Deposited: 22 Apr 2013 06:38
Last Modified: 22 Apr 2013 06:38
URI: http://eprints.iisc.ac.in/id/eprint/46444

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