Row-buffer reorganization: simultaneously improving performance and reducing energy in DRAMs

Gulur, Nagendra and Manikantan, R and Govindarajan, Ramaswamy and Mehendale, Mahesh M (2011) Row-buffer reorganization: simultaneously improving performance and reducing energy in DRAMs. In: 2011 International Conference on Parallel Architectures and Compilation Techniques (PACT), 10-14 Oct. 2011, Galveston, TX.

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Abstract

In this paper, based on the temporal and spatial locality characteristics of memory accesses in multicores, we propose a re-organization of the existing single large row buffer in a DRAM bank into multiple smaller row-buffers. The proposed configuration helps improve the row hit rates and also brings down the energy required for row-activations. The major contribution of this work is proposing such a reorganization without requiring any significant changes to the existing widely accepted DRAM specifications. Our proposed reorganization improves performance by 35.8%, 14.5% and 21.6% in quad, eight and sixteen core workloads along with a 42%, 28% and 31% reduction in DRAM energy. Additionally, we introduce a Need Based Allocation scheme for buffer management that shows additional performance improvement.

Item Type:	Conference Paper
Publisher:	IEEE
Additional Information:	Copyright of this article belongs to IEEE.
Keywords:	DRAM; Multicore; Row-Buffer Organization
Department/Centre:	Division of Electrical Sciences > Computer Science & Automation
Date Deposited:	19 Mar 2013 05:28
Last Modified:	19 Mar 2013 05:28
URI:	http://eprints.iisc.ac.in/id/eprint/46028

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