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Exploiting the Structure of the Constraint Graph for Efficient Points-to Analysis

Nasre, Rupesh (2012) Exploiting the Structure of the Constraint Graph for Efficient Points-to Analysis. In: ACM SIGPLAN NOTICES, 47 (11). pp. 121-132.

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Official URL: http://dx.doi.org/10.1145/2426642.2259013

Abstract

Points-to analysis is a key compiler analysis. Several memory related optimizations use points-to information to improve their effectiveness. Points-to analysis is performed by building a constraint graph of pointer variables and dynamically updating it to propagate more and more points-to information across its subset edges. So far, the structure of the constraint graph has been only trivially exploited for efficient propagation of information, e.g., in identifying cyclic components or to propagate information in topological order. We perform a careful study of its structure and propose a new inclusion-based flow-insensitive context-sensitive points-to analysis algorithm based on the notion of dominant pointers. We also propose a new kind of pointer-equivalence based on dominant pointers which provides significantly more opportunities for reducing the number of pointers tracked during the analysis. Based on this hitherto unexplored form of pointer-equivalence, we develop a new context-sensitive flow-insensitive points-to analysis algorithm which uses incremental dominator update to efficiently compute points-to information. Using a large suite of programs consisting of SPEC 2000 benchmarks and five large open source programs we show that our points-to analysis is 88% faster than BDD-based Lazy Cycle Detection and 2x faster than Deep Propagation. We argue that our approach of detecting dominator-based pointer-equivalence is a key to improve points-to analysis efficiency.

Item Type: Journal Article
Additional Information: Copyright for this article belongs to ASSOC COMPUTING MACHINERY,NEW YORK,
Keywords: Algorithms;Languages;constraint graph;dominators;points-to analysis;context-sensitivity
Department/Centre: Division of Electrical Sciences > Computer Science & Automation
Depositing User: Francis Jayakanth
Date Deposited: 19 Feb 2013 05:12
Last Modified: 19 Feb 2013 05:12
URI: http://eprints.iisc.ac.in/id/eprint/45831

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