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A simple and fast scheme for code compression for VLIW processors

Prakash, J and Sandeep, C and Shankar, P and Srikant, YN (2003) A simple and fast scheme for code compression for VLIW processors. In: Proceedings. DCC 2003 Data Compression Conference, 2003. , 25-27 March 2003.

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Summary form only given. A scheme for code compression that has a fast decompression algorithm, which can be implemented using simple hardware, is proposed. The effectiveness of the scheme on the TMS320C62x architecture that includes the overheads of a line address table (LAT) is evaluated and obtained compression rates ranging from 70% to 80%. Two schemes for decompression are proposed. The basic idea underlying the scheme is a simple clustering algorithm that partially maps a block of instructions into a set of clusters. The clustering algorithm is a greedy algorithm based on the frequency of occurrence of various instructions.

Item Type: Conference Paper
Publisher: IEEE
Additional Information: Copyright 2003 IEEE. Personal use of this material is permitted.However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Electrical Sciences > Computer Science & Automation
Date Deposited: 16 Mar 2012 12:13
Last Modified: 16 Mar 2012 12:13
URI: http://eprints.iisc.ac.in/id/eprint/43948

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