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Continous Time Sigma-Delta Modulator Employing a Novel Comparator Architecture

Vijay, UK and Bharadwaj, Amrutur (2007) Continous Time Sigma-Delta Modulator Employing a Novel Comparator Architecture. In: 20th International Conference on VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 6-10 Jan. 2007 , Bangalore.

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A novel comparator architecture is proposed for speed operation in low voltage environment. Performance comparison with a conventional regenerative comparator shows a speed-up of 41%. The proposed comparator is embedded in a continuous time sigma-delta ADC so as to reduce the quantizer delay and hence minimizes the excess loop delay problem. A performance enhancement of 1dB in the dynamic range of the ADC is achieved with this new comparator. We have implemented this ADC in a standard single-poly 8-Metal 0.13 mum UMC process. The entire system operates at 1.2 V supply providing a dynamic range of 32 dB consuming 720 muW of power and occupies an area of 0.1 mm2.

Item Type: Conference Paper
Publisher: IEEE
Additional Information: Copyright 2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited: 14 Oct 2011 09:38
Last Modified: 14 Oct 2011 09:38
URI: http://eprints.iisc.ac.in/id/eprint/41455

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