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Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach

Tudu, JT and Larsson, E and Singh, V and Fujiwara, H (2009) Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach. In: 10th IEEE Workshop on RTL and High Level Test (WRTLT), Nov 2009, Praha, Czech Republic .

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Abstract

Scan circuit is widely practiced DFT technology. The scan testing procedure consist of state initialization, test application, response capture and observation process. During the state initialization process the scan vectors are shifted into the scan cells and simultaneously the responses captured in last cycle are shifted out. During this shift operation the transitions that arise in the scan cells are propagated to the combinational circuit, which inturn create many more toggling activities in the combinational block and hence increases the dynamic power consumption. The dynamic power consumed during scan shift operation is much more higher than that of normal mode operation.

Item Type: Conference Paper
Additional Information: Copyright 2009 IEEE. Personal use of this material is permitted.However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Interdisciplinary Research > Supercomputer Education & Research Centre
Depositing User: Ms TV Yashodha
Date Deposited: 09 Dec 2011 11:51
Last Modified: 09 Dec 2011 11:51
URI: http://eprints.iisc.ac.in/id/eprint/41273

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