Subramanyan, Pramod and Singh, Virendra and Saluja, Kewal K (2009) Power Efficient Redundant Execution for Chip Multiprocessor. In: Workshop on Dependable and Secure Nanocomputing (WDSN) 2009, June 2009, Lisbon, Portugal.
PDF
FULLTEXT01.pdf - Published Version Restricted to Registered users only Download (269kB) | Request a copy |
Abstract
This paper describes the design of a power efficient microarchitecture for transient fault detection in chip multiprocessors (CMPs) We introduce a new per-core dynamic voltage and frequency scaling (DVFS) algorithm for our architecture that significantly reduces power dissipation for redundant execution with a minimal performance overhead. Using cycle accurate simulation combined with a simple first order power model, we estimate that our architecture reduces dynamic power dissipation in the redundant core by an mean value of 79% and a maximum of 85% with an associated mean performance overhead of only 1:2%
Item Type: | Conference Paper |
---|---|
Department/Centre: | Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre |
Date Deposited: | 14 Dec 2011 12:03 |
Last Modified: | 14 Dec 2011 12:08 |
URI: | http://eprints.iisc.ac.in/id/eprint/41256 |
Actions (login required)
View Item |