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Hardware implementation of 4x4 DCT/Quantization block using multiplication and error-free algorithm

Nandi, Suvam and Rajan, K and Biswas, Prasenjit (2009) Hardware implementation of 4x4 DCT/Quantization block using multiplication and error-free algorithm. In: TENCON, 23-26 Nov 2009, Singapore.

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The 4ÃÂ4 discrete cosine transform is one of the most important building blocks for the emerging video coding standard, viz. H.264. The conventional implementation does some approximation to the transform matrix elements to facilitate integer arithmetic, for which hardware is suitably prepared. Though the transform coding does not involve any multiplications, quantization process requires sixteen 16-bit multiplications. The algorithm used here eliminates the process of approximation in transform coding and multiplication in the quantization process, by usage of algebraic integer coding. We propose an area-efficient implementation of the transform and quantization blocks based on the algebraic integer coding. The designs were synthesized with 90 nm TSMC CMOS technology and were also implemented on a Xilinx FPGA. The gate counts and throughput achievable in this case are 7000 and 125 Msamples/sec.

Item Type: Conference Paper
Additional Information: Copyright 2009 IEEE. Personal use of this material is permitted.However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Physical & Mathematical Sciences > Physics
Depositing User: Ms TV Yashodha
Date Deposited: 16 Dec 2011 09:17
Last Modified: 16 Dec 2011 09:17
URI: http://eprints.iisc.ac.in/id/eprint/41192

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