ePrints@IIScePrints@IISc Home | About | Browse | Latest Additions | Advanced Search | Contact | Help

On synthesis of easily testable (k, K) circuits

Naidu, Srinath R and Chandru, Vijay (2003) On synthesis of easily testable (k, K) circuits. In: IEEE Transactions on Computers, 52 (11). pp. 1490-1494.

[img] PDF
On_Synthesis_of.pdf - Published Version
Restricted to Registered users only

Download (412kB) | Request a copy
Official URL: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumb...


A (k-, K) circuit is one which can be decomposed into nonintersecting blocks of gates where each block has no more than K external inputs, such that the graph formed by letting each block be a node and inserting edges between blocks if they share a signal line, is a partial k-tree. (k, K) circuits are special in that they have been shown to be testable in time polynomial in the number of gates in the circuit, and are useful if the constants k and K are small. We demonstrate a procedure to synthesise (k, K) circuits from a special class of Boolean expressions.

Item Type: Journal Article
Publication: IEEE Transactions on Computers
Publisher: IEEE
Additional Information: Copyright 2003 IEEE. Personal use of this material is permitted.However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Keywords: Testing;stuck-at fault;polynomial time;k-tree;treewidth; synthesis.
Department/Centre: Division of Electrical Sciences > Computer Science & Automation
Date Deposited: 25 Aug 2011 09:32
Last Modified: 25 Aug 2011 09:32
URI: http://eprints.iisc.ac.in/id/eprint/40157

Actions (login required)

View Item View Item