ePrints@IIScePrints@IISc Home | About | Browse | Latest Additions | Advanced Search | Contact | Help

Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions

Varadarajan, Keshavan and Nandy, SK and Sharda, Vishal and Bharadwaj, Amrutur and Iyer, Ravi and Makineni, Srihari and Newell, Donald (2006) Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions. In: 39th Annual IEEE/ACM International Symposium on Microarchitecture,, Dec 09-13, 2006, Orlando, FL, pp. 433-442.

[img] PDF
04041866.pdf - Published Version
Restricted to Registered users only

Download (179kB) | Request a copy
Official URL: http://ieeexplore.ieee.org/search/srchabstract.jsp...

Abstract

CMPs enable simultaneous execution of multiple applications on the same platforms that share cache resources. Diversity in the cache access patterns of these simultaneously executing applications can potentially trigger inter-application interference, leading to cache pollution. Whereas a large cache can ameliorate this problem, the issues of larger power consumption with increasing cache size, amplified at sub-100nm technologies, makes this solution prohibitive. In this paper in order to address the issues relating to power-aware performance of caches, we propose a caching structure that addresses the following: 1. Definition of application-specific cache partitions as an aggregation of caching units (molecules). The parameters of each molecule namely size, associativity and line size are chosen so that the power consumed by it and access time are optimal for the given technology. 2. Application-Specific resizing of cache partitions with variable and adaptive associativity per cache line, way size and variable line size. 3. A replacement policy that is transparent to the partition in terms of size, heterogeneity in associativity and line size. Through simulation studies we establish the superiority of molecular cache (caches built as aggregations of molecules) that offers a 29% power advantage over that of an equivalently performing traditional cache.

Item Type: Conference Paper
Series.: INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, PROCEEDINGS
Publisher: Institute of Electrical and Electronics Engineers
Additional Information: Copyright 2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Electrical Sciences > Electrical Communication Engineering
Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited: 31 Aug 2010 08:36
Last Modified: 08 Jul 2011 07:15
URI: http://eprints.iisc.ac.in/id/eprint/30470

Actions (login required)

View Item View Item