RETHROTTLE: Execution Throttling in the REDEFINE SoC Architecture

Satrawala, AN and Nandy, SK (2009) RETHROTTLE: Execution Throttling in the REDEFINE SoC Architecture. In: Systems, Architectures, Modeling, and Simulation, 2009. SAMOS '09. International Symposium on, JUL 20-23, 2009, Samos, pp. 82-91.

PDF rethro.pdf - Published Version Restricted to Registered users only Download (1MB) | Request a copy

Abstract

REDEFINE is a reconfigurable SoC architecture that provides a unique platform for high performance and low power computing by exploiting the synergistic interaction between coarse grain dynamic dataflow model of computation (to expose abundant parallelism in applications) and runtime composition of efficient compute structures (on the reconfigurable computation resources). We propose and study the throttling of execution in REDEFINE to maximize the architecture efficiency. A feature specific fast hybrid (mixed level) simulation framework for early in design phase study is developed and implemented to make the huge design space exploration practical. We do performance modeling in terms of selection of important performance criteria, ranking of the explored throttling schemes and investigate effectiveness of the design space exploration using statistical hypothesis testing. We find throttling schemes which give appreciable (24.8%) overall performance gain in the architecture and 37% resource usage gain in the throttling unit simultaneously.

Item Type:	Conference Paper
Publisher:	IEEE
Additional Information:	Copyright 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Keywords:	Hybrid Simulation; Reconfigurable; SoC; Dataflow; Throttling; Performance Evaluation; Ranking
Department/Centre:	Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited:	26 Apr 2010 08:41
Last Modified:	19 Sep 2010 06:00
URI:	http://eprints.iisc.ac.in/id/eprint/27262

Actions (login required)

View Item