Modeling and Analysis of Noise Margin in SET Logic

Sathe, Chaitanya and Mahapatra, Santanu (2007) Modeling and Analysis of Noise Margin in SET Logic. In: 20th International Conference on VLSI Design held jointly with the 6th International Conference on Embedded Systems, JAN 06-10, 2007, Bangalore.

PDF ieeet.pdf - Published Version Restricted to Registered users only Download (946kB) | Request a copy

Abstract

In this paper the static noise margin for SET (single electron transistor) logic is defined and compact models for the noise margin are developed by making use of the MIB (Mahapatra-Ionescu-Banerjee) model. The variation of the noise margin with temperature and background charge is also studied. A chain of SET inverters is simulated to validate the definition of various logic levels (like VIH, VOH, etc.) and noise margin. Finally the noise immunity of SET logic is compared with current CMOS logic.

Item Type:	Conference Paper
Publisher:	IEEE
Additional Information:	Copyright 2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre:	Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited:	10 Jun 2010 09:46
Last Modified:	02 Nov 2011 05:27
URI:	http://eprints.iisc.ac.in/id/eprint/26737

Actions (login required)

View Item