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Latency, Power and Performance Trade-offs in Network-on-Chips by Link Microarchitecture Exploration

Talwar, Basavaraj and Kulkarni, Shailesh and Amrutur, Bharadwaj (2009) Latency, Power and Performance Trade-offs in Network-on-Chips by Link Microarchitecture Exploration. In: 22nd International Conference on VLSI Design, 5-9 Jan. 2009, New Delhi, INDIA, pp. 163-168.

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This paper presents a power, latency and throughput trade-off study on NoCs by varying microarchitectural (e.g. pipelining) and circuit level (e.g. frequency and voltage) parameters. We change pipelining depth, operating frequency and supply voltage for 3 example NoCs - 16 node 2D Torus, Tree network and Reduced 2D Torus. We use an in-house NoC exploration framework capable of topology generation and comparison using parameterized models of Routers and links developed in SystemC. The framework utilizes interconnect power and delay models from a low-level modelling tool called Intacte[1]1. We find that increased pipelining can actually reduce latency. We also find that there exists an optimal degree of pipelining which is the most energy efficient in terms of minimizing energy-delay product.

Item Type: Conference Paper
Additional Information: Copyright 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Electrical Sciences > Electrical Communication Engineering
Depositing User: Id for Latest eprints
Date Deposited: 28 Aug 2009 15:02
Last Modified: 19 Sep 2010 05:30
URI: http://eprints.iisc.ac.in/id/eprint/19897

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