Functional Test Generation for Non-Scan Sequential Circuits

Srinivas, MK and Jacob, James and Agrawal, Vishwani D (1995) Functional Test Generation for Non-Scan Sequential Circuits. In: 8th International Conference on VLSI Design, 1995, 4-7 January 1995, New Delhi, India, pp. 47-52.

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Abstract

The feasibility of generating high quality functional test vectors for sequential circuits using the Growth (G) and Disappearance (D) fault model has been demonstrated earlier. In this paper we provide a theoretical validation of the G and D fault model by proving the ability of this model to guarantee complete stuck fault coverage in combinational and sequential circuits synthesized employing algebraic transformations. We also provide experimental results on a wide range of synthesized FSMs. A comparison with a state-of-the-art gate level ATPG tool demonstrates the efficiency and limitation of the functional approach.

Item Type:	Conference Paper
Publisher:	IEEE
Additional Information:	1995 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre:	Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited:	25 Aug 2008
Last Modified:	19 Sep 2010 04:37
URI:	http://eprints.iisc.ac.in/id/eprint/10822

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