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On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface Methodology

Harish, BP and Bhat, Navakanta and Patil, Mahesh B (2007) On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface Methodology. In: IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems, 26 (3). pp. 606-614.


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Ageneralized methodology formodeling the effects of process variations on circuit delay performance is proposed by directly relating the variations in process parameters to variations in delay metric of a digital circuit. The 2-input NAND gate is used as a library element for 65 nm gate length technology, whose delay is extensively characterized by mixedmode simulations. This information is then used in a general-purpose circuit simulator SEQUEL, by incorporating appropriate templates for the NAND gate library. A 4-bit × 4-bit Wallace tree multiplier circuit, consisting of about 300 2-input NAND gates, is used as a representative combinational circuit to demonstrate the proposed methodology. The variation in the multiplier delay is characterized by an extensive Monte Carlo analysis. To extend this methodology for a generic technology library with a variety of library elements, odeling of NAND gate delays by response surface methodology (RSM), in terms of process parameters, is carried out using design of experiments (DOE). A simple piecewise quadratic model, based on the least squares method (LSM), is proposed for one-parameter variation to address significant cubic effects observed in the delay response function. Then, a hybrid model for gate delays is generated by superimposing the interaction terms of DOE–RSM model upon the quadratic model of one-parameter variation to address the generalized case of simultaneous variations in multiple process parameters. The proposed methodology has been demonstrated for NAND gate library with 266 gates, and the simplicity and generality of the approachmake it equally applicable to a large library of cells for both statistical timing analysis and statistical circuit simulation at the gate level.

Item Type: Journal Article
Additional Information: Copyright 2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Keywords: Delay distribution;Design of experiments (DOE);Hybrid model;Least squares method (LSM);Mixed-mode simulations;Monte Carlo analysis;Process sensitivity;Response surface methodology (RSM)
Department/Centre: Division of Electrical Sciences > Electrical Communication Engineering
Depositing User: Sumana K
Date Deposited: 25 Aug 2008
Last Modified: 19 Sep 2010 04:36
URI: http://eprints.iisc.ac.in/id/eprint/10562

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